1. Field of the Invention
The present invention generally relates to non-volatile semiconductor memory devices and internal operation methods for the same. More particularly, the present invention relates to a non-volatile semiconductor memory device which is electrically erasable and writable, such as a flash memory, and also to an internal operation method for such a non-volatile semiconductor memory device.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing an example of a conventional non-volatile semiconductor memory device which is electrically erasable and programmable. In this figure, reference numeral 1 indicates a memory cell array in which non-volatile memory cells consisting of electrically erasable and programmable stacked-gate-type n-channel MOS transistors are arranged. Reference numeral 2 indicates a command register circuit which receives commands from outside, and reference numeral 3 indicates a pre-program/erase control circuit which controls pre-program/erase in the memory cell array 1 when the command register circuit 2 receives an erase command. Reference numeral 4 indicates a booster circuit which generates a boosted voltage, and reference numeral 5 indicates a voltage limiter circuit which limits the voltage value of the boosted voltage outputted from the booster circuit 4, and which steadily outputs high voltages VPP/-VPP necessary for performing program/erase in the non-volatile memory cells in the memory cell array 1.
FIG. 2 is a schematic sectional view of a non-volatile memory cell in the memory cell array 1. In this figure, reference numeral 7 indicates a P-type well, reference numeral 8 indicates a source that is an N-type diffused layer, reference numeral 9 indicates a drain that is also an N-type diffused layer, reference numeral 10 indicates a control gate, and reference numeral 11 indicates a floating gate.
FIG. 3 is a table showing the control gate voltage, source voltage, and drain voltage when program, erase, and read is performed in the non-volatile memory cells in the memory cell array 1.
At the time of program, the control gate voltage is equal to a program high voltage VPP (10 V, for instance), the source voltage is equal to a ground voltage (0 V), and the drain voltage is equal to a power source voltage VCC (5 V, for instance). Electrons are injected from the drain 9 into the floating gate 11, and "0" is stored.
At the time of erase, the control gate voltage is equal to an erase high voltage -VPP (-10 V, for instance), the source voltage is equal to the power source voltage VCC (5 V, for instance), and the drain voltage is in an open state. Here, electrons are withdrawn from the floating gate 11 toward the source 8, and "1" is stored.
At the time of read, the control gate voltage is equal to the power source voltage VCC (5 V, for instance), the source voltage is equal to the ground voltage VSS (0 V), and the drain voltage is +2 V. Here, the stored data is read out as the size of the drain current.
FIGS. 4A to 4C illustrates an erase operation in the non-volatile memory cells in the memory cell array 1. FIG. 4A shows the stored data in the non-volatile memory cells in the memory cell array 1 before erase, FIG. 4B shows the stored data after pre-program, FIG. 4C shows the stored data after erase.
Before erase is performed in the non-volatile memory cells in the memory cell array 1, "0" is written in all the non-volatile memory cells as the pre-program process. The erase is then performed in all the non-volatile memory cells, and "1" is inputted into all the non-volatile memory cells.
FIG. 5 shows the relationship between the number of program/erase cycles and the erasing time in the no-volatile memory cells in the memory cell array 1. As the number of program/erase cycles in the non-volatile memory cells increases, the erasing time becomes longer due to deterioration of the tunnel oxide film or an electron trap in the tunnel oxide film.
FIG. 6 shows the relationship among a program/erase high voltage .+-.VPP, the number of program/erase cycles in the non-volatile memory cells, the erasing time, and the lives of the non-volatile memory cells. In this figure, a line 13 indicates a case where the program/erase high voltage .+-.VPP is normal, a line 14 indicates a case where the program/erase high voltage .+-.VPP is higher than the normal program/erase high voltage .+-.VPP, and a line 15 indicates a case where the program/erase high voltage .+-.VPP is lower than the normal program/erase high voltage .+-.VPP. Points "X" indicate when the non-volatile memory cells break down.
As can be seen from FIG. 6, in the case where the program/erase high voltage .+-.VPP is higher than the normal program/erase high voltage .+-.VPP, the erasing time can be shortened, thereby realizing high-speed erasing operation. However, there is a problem that the lives of the non-volatile memory cells become very short.
It should be understood here that, throughout the present specification, "increasing the erase high voltage -VPP" means increasing the absolute value of the erase high voltage -VPP, and "reducing the erase high voltage -VPP" means reducing the absolute value of the erase high voltage -VPP.
Meanwhile, as the number of program/erase cycles in the non-volatile memory cells, the reliability of the non-volatile memory cells deteriorates due to the deterioration of the tunnel oxide film or the electron trap in the tunnel oxide film. In view of this, in a case where the number of program/erase cycles in the non-volatile memory cells is larger than a predetermined value, the high voltage VPP is reduced, and the stress applied to the non-volatile memory cells is reduced to prevent a decrease in the reliability of the non-volatile memory cells. In such a case, however, it should be understood that the erasing time becomes longer.